At present, as described in Patent Document 1, for example, the optical transmission system employs a time division multiplexing system in which a plurality of low-speed digital signals are multiplexed in a time division manner to form one high-speed digital signal (which may be referred to as high-speed transmission signal) and the high-speed transmission signal is transmitted in an optical fiber in order to economically transmit the digital signal to a destination. Further, in the transmission of this type, framing is performed in multiple layers by multilayered frames and a stuff processing is performed per layer as follows as needed.
Each low-speed digital signal is multiplexed in a stuff multiplexing system or the like in order to multiplex a plurality of low-speed digital signals in a time division manner. In the stuff multiplexing system, the low-speed digital signal as client data at the transmission side is mapped in a frame form according to a clock signal having a predetermined frequency. During the mapping, there is performed a stuff processing of inserting a stuff pulse having no information component into each low-speed digital signal. There is performed a destuff processing of demapping the signal in the frame format the reception side to recover the client data and of removing the stuff pulse during the recovering.
When there is performed a demapping processing of extracting N clocks' client data in line data from the M clock's line data transmitted in a multilayered frame form, a clock signal is recovered from the line data and the client data in the line data is written in a buffer memory by the recovered clock signal. The written client data is read and recovered by an oscillation clock signal of an oscillator synchronized with the recovered clock signal. M and N for M clocks and N clocks are positive integers and have the relationship of N<M.
Further, when a clock signal is recovered from the line data during the demapping, a signal for clock recovery needs to be generated, which is formed by alternately generating enable periods having a ratio (N/M) of the N clock's client data to the M clock's line data, and disable periods. In FIG. 1, a signal for clock recovery ED is input into a clock recovery circuit 20, thereby obtaining a recovered clock signal CK.
The clock recovery circuit 20 is configured to include a phase comparator circuit 22 as phase synchronization loop circuit, a LPF (lowpass filter) 23 and a VCO (voltage control oscillator) 24. The signal for clock recovery ED is input into the phase comparator circuit 22 of the clock recovery circuit 20, the signal for clock recovery ED and the fed-back recovered clock signal CK are compared with each other for their phases in the phase comparator circuit 22, and a differential signal obtained from the comparison result is output to the LPF 23.
Further, a voltage signal obtained by filtering the differential signal in the LPF 23 is supplied to the VCO 24 and the recovered clock signal CK having a frequency according to the voltage supply is output. The N clocks' client data in the M clocks' line data is written in the buffer memory by the recovered clock signal CK. Furthermore, the client data written in the buffer memory is read and recovered by the oscillation clock signal of the oscillator synchronized with the recovered clock signal CK.
When the demapping processing is performed in this manner, if a stuff pulse is inserted in the line data, the destuff processing is also performed. In the destuff processing, during the destuff detection for detecting a stuff pulse inserted in the multilayered line data, in order to remove the stuff pulse, that is, in order to prevent the stuff pulse from being written in the buffer memory, a disable period is added to the signal for clock recovery ED.
The adding processing will be described with reference to a timing chart shown in FIG. 2. FIG. 2(a) shows an enable generation cycle EC in which one cycle is sequentially repeated at a cycle timing value of “0, 1, 2, 3, 4”, FIG. 2(b) shows a signal for clock recovery ED1 which is formed by alternately generating the enable periods EN and the disable periods D when a stuff pulse is not detected in the destuff processing, and FIG. 2(c) shows a signal for clock recovery ED2 which is formed by alternately generating the enable periods EN and the disable periods D when a stuff pulse is detected in the destuff processing. The cycle timing corresponds to one clock reproduced from the line data.
In other words, when a stuff pulse is not detected, as shown in FIG. 2(b), there is generated the disable period D having the “L” level for one clock with the cycle timing value of “0” per five clocks (which will be abbreviated to “L”), and there is generated the enable period EN having the “H” level for four clocks with other cycle timing value of “1, 2, 3, 4” (which will be abbreviated to “H”).
On the other hand, as shown in FIG. 2(c), when a stuff pulse is detected, the stuff pulse is detected at time t10, for example, and the disable period D is generated and added at the cycle timing of “4” for one clock between time t10 and t11.
In the case of the multilayered frame, a frequency dividing counter (not shown) is used to cause the frequency dividing counter to count such that a count value CT is repeated in the order of “0, 1, 2” as shown in FIG. 3(d) when the cycle timing value of the enable generation cycle EC in FIG. 3(a) is “1, 2, 3, 4” and the signal for clock recovery ED2 in FIG. 3(c) is at “H”. When the count value CT is at “1, 2”, the enable period EN is generated to be “H” as shown in FIG. 3(e) and thereby a signal for clock recovery ED3 is generated.